Integrated circuit designers often desire to increase the level of integration or density of elements within an integrated circuit by reducing the size of the individual elements and by reducing the separation distance between neighboring elements. In addition, integrated circuit designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
A relatively common integrated circuit device is a memory device. A memory device may include a memory array having a number of memory cells arranged in a grid pattern. One type of memory cell is a resistive memory cell, such as a resistive random access memory (RRAM) cell, which stores data by switching between electrical resistance states. For example, for binary data storage, a high-resistance state of the resistive memory cell may be read as logical “1,” while a low-resistance state of the resistive memory cell may be read as logical “0.” Switching between resistance states may be achieved by applying different physical signals (e.g., voltage, current, etc.) across the resistive memory cell.
There is continuing interest in the development of methodologies by which memory cell (e.g., resistive memory cell) dimensions can be scaled down to realize higher density memory devices (e.g., resistive memory devices) and form higher capacity electronic devices and systems. Unfortunately, scaling down memory cell dimensions to increase memory device density can result in problems, such as undesirable electrical coupling effects.
It would, therefore, be desirable to have improved methods and structures that facilitate scaling down memory cell dimensions to form higher density memory devices while mitigating problems (e.g., adverse electrical coupling effects) conventionally associated with scaling down memory cell dimensions to form higher density memory devices.